A yield-optimized latch-type SRAM sense amplifier

Author

Wicht, Bernhard ; Nirschl, Thomas ; Schmitt-Landsiede, Doris

Author_Institution

Texas Instruments, Freising, Germany

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

409

Lastpage

412

Abstract

A yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It quantifies the impact of supply voltage, input dc level, transistor sizing and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived. Experimental results in 130nm CMOS confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19mV to 8.5mV without affecting the delay which is measured to be 119ps at 1.5V supply.

Keywords

CMOS integrated circuits; SRAM chips; VLSI; amplifiers; delays; 1.5 V; 119 ps; 130 nm; 19 to 8.5 mV; CMOS; SRAM; analytical expression; high-impedance input stage; input dc level; input offset voltage; latch-type voltage; offset standard deviation; sense amplifier; sensing delay; supply voltage; temperature; transistor sizing; yield analysis; Coupling circuits; Delay effects; Flip-flops; Instruments; Inverters; Latches; Random access memory; Temperature sensors; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257159

Filename

1257159