Wirelength driven floorplacement for FPGA-based partial reconfigurable systems

The proposed work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities and wirelength. The proposed floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, uses an objective function based on external wirelength, i.e., the estimated length of the nets connecting each Reconfigurable Functional Unit to the corresponding required chip Input Output Blocks. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of re-use of existing links (90% reduction can be obtained in the best case).