A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks

Author

Lee, Kangmin ; Lee, Se-Joong ; Yoo, Hoi-Jun

Author_Institution

Semicond. Syst. Lab., KAIST, Dajeon, South Korea

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

453

Lastpage

456

Abstract

In this paper, we propose and analyze a high-speed and area-efficient crossbar scheduling algorithm for o-chip interconnection networks. The algorithm is based on a distributed computing over crossbar fabric while conventional algorithms such as round robin are centralized apart from crossbar fabric. Its implementation shows that it can reduce scheduling delay and its area more than 20% and 50%, respectively a compared to a round robin based SLIP algorithm. We apply the algorithm to a HDTV SoC to analyze its feasibility. The proposed algorithm and its implementation are area-efficient and show higher performance for the on-chip interconnection networks.

Keywords

electronic switching systems; integrated circuit interconnections; multiprocessor interconnection networks; processor scheduling; queueing theory; system-on-chip; HDTV SoC; SLIP algorithm; chip crossbar switch scheduler; crossbar fabric; crossbar scheduling algorithm; distributed computing; on-chip interconnection networks; round robin; scheduling delay; Algorithm design and analysis; Delay; Distributed computing; Fabrics; Multiprocessor interconnection networks; Network-on-a-chip; Processor scheduling; Round robin; Scheduling algorithm; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257170

Filename

1257170