Title :
A 10Gbps/port 8/spl times/8 shared bus switch with embedded DRAM hierarchical output buffer
Author :
Lee, Kangmin ; Lee, Se-Joong ; Hoi-Jun Yoo
Author_Institution :
Semicond. Syst. Lab., KAIST, Daejon, South Korea
Abstract :
A hierarchical buffering technique with the embedded DRAM (eDRAM) as a packet buffer is proposed for 10Gbps/port 8/spl times/8 shared bus switch. A prototype chip with 8 input ports and an output port is implemented by 0.16/spl mu/m DRAM technology. To satisfy the required buffering capacity and memory bandwidth of 90Gbps, a 200MHz 32kb SRAM and four 25MHz 1 Mb eDRAM macros are used hierarchically with 512bit interface. The die area is 13.8mm/sup 2/ including SRAM and DRAM.
Keywords :
CMOS memory circuits; DRAM chips; SRAM chips; embedded systems; system-on-chip; 10Gbps/port; 512bit interface; DRAM hierarchical output buffer; DRAM technology; SRAM; buffering capacity; hierarchical buffering; memory bandwidth; packet buffer; prototype chip; shared bus switch; Bandwidth; Capacity planning; Costs; Delay; Laboratories; Packet switching; Quality of service; Random access memory; Semiconductor device measurement; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257172
