A simple design methodology for increased ESD robustness of CMOS core cells

Author

Huitsing, A.J. ; Smedes, T. ; Schröder, H.U.

Author_Institution

Philips Semicond. Nijmegen, Netherlands

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

481

Lastpage

484

Abstract

Certain ESD failures are caused by the destruction of a single NMOST finger in a core cell. This can be avoided by making the NMOST fingers wide enough to handle the current from the above lying PMOST(s) during an ESD event. The observed failure mechanism is discussed and a model is presented that can predict the critical PMOST width to NMOST finger width ratio for a CMOS core cell. The model has been examined with experiments in a 0.25 /spl mu/m CMOS technology. A straightforward design method is proposed to improve the ESD robustness of core cells for a given CMOS technology and ESD protection library.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit design; integrated circuit modelling; integrated circuit reliability; 0.25 micron; CMOS core cells; CMOS technology; ESD failures; ESD protection library; ESD robustness; PMOST width; electrostatic discharge; failure mechanism; single NMOST finger; CMOS technology; Design methodology; Electrostatic discharge; Failure analysis; Fingers; Libraries; Predictive models; Protection; Robustness; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257177

Filename

1257177