A 19.2GOPS, 20mW adaptive FIR filter

Author

Figueroa, Miguel ; Bridges, Seth ; Hsu, David ; Diorio, Chris

Author_Institution

Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

509

Lastpage

512

Abstract

We implemented a 48-tap, mixed signal adaptive FIR filter with 8-bit input and 10-bit output resolution. The filter stores its tap weights in nonvolatile analog memory cells and adapts using the least-mean-square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulsed-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in an 0.35/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200MHz, and consumes 20mW providing a 6mA differential output current.

Keywords

CMOS integrated circuits; FIR filters; adaptive filters; delay lines; least mean squares methods; mixed analogue-digital integrated circuits; 0.35 micron; 20 mW; 200 MHz; adaptive FIR filter; analog tap weights; digital tapped delay line; digital words; least-mean-square algorithm; mixed signal filter; mixed-signal multipliers; nonvolatile analog memory cells; pulsed-based feedback; tap coefficients; Adaptive filters; Bridge circuits; Computer architecture; Computer science; Delay lines; Digital filters; Finite impulse response filter; Least squares approximation; Memory architecture; Nonvolatile memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257184

Filename

1257184