Title :
An embedded core for the 2D wavelet transform
Author :
Diou, Camille ; Torres, Lionel ; Robert, Michel
Author_Institution :
CESIUM, LICM, Metz, France
Abstract :
We present a new architecture for the wavelet transform based on the lifting scheme. We present the advantages of the lifting scheme compared to the filter-bank method and propose an architecture that allows a high processing rate and has a very small memory requirement. A new way of managing the transposition buffer using FIFO and delay lines allows the 2D decomposition of an image in real time on-the-fly. The proposed architecture is therefore very compact and is adapted for an implementation as a macrocell inside a system-on-a-chip.
Keywords :
buffer storage; computer architecture; delay lines; digital signal processing chips; embedded systems; image processing equipment; wavelet transforms; 2D wavelet transform architecture; FIFO scheme; delay lines; embedded core; filter banks; lifting scheme; macrocell; memory requirement; processing rate; real-time on-the-fly 2D image decomposition; system on chip; transposition buffer management; Computer architecture; Delay lines; Digital signal processing chips; Filter bank; Macrocell networks; Signal processing algorithms; Silicon; System-on-a-chip; Wavelet analysis; Wavelet transforms;
Conference_Titel :
Emerging Technologies and Factory Automation, 2001. Proceedings. 2001 8th IEEE International Conference on
Conference_Location :
Antibes-Juan les Pins, France
Print_ISBN :
0-7803-7241-7
DOI :
10.1109/ETFA.2001.997684
