Analytical performance comparison of 2D Mesh, WK-recursive, and Spidergon NoCs

Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulation which becomes computationally expensive, especially for large-scale NoCs. Recently, a Network Calculus-based methodology was proposed to analytically evaluate the performance of NoC-based architectures. In this paper, the 2D Mesh, Spidergong, and WK-recursive on-chip interconnects are analyzed using this methodology and main performance metrics, the end-to-end delay and buffer size requirements, are computed. Results are reported and show that WK outperforms the other on-chip interconnects in all considered performance metrics.