Embedded test for a new memory-card architecture

Author

Resnick, David

Author_Institution

Cray Inc., Chippewa Falls, WI, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

875

Lastpage

882

Abstract

Requirements for a new Cray Inc. computer system mean that the system´s memory cards have high-speed SerDes interfaces and multiple memory controllers in a semicustom IC close to the memory chips. As a result, the functionality of a card is much greater than is current practice, and the cards can not be connected to existing memory testers. An embedded test system is designed for the card that can test all aspects of the card including the SerDes paths, a large L3 cache, the memory controllers, and the memory parts mounted on the cards, with testing driven from a JTAG port. The test capability is based in a microcoded controller, with data packets being generated and checked rather than directly controlling the logic being exercised. Some of the test implementation discussed here is patent pending.

Keywords

Cray computers; embedded systems; integrated circuit testing; logic testing; memory architecture; memory cards; microcontrollers; peripheral interfaces; Cray computer system; JTAG port; data packets; embedded test system; high speed serializer deserializer interfaces; joint test action group standard; logic control; logic testing; memory card architecture; memory chips; memory testers; microcoded controller; multiple memory controllers; semicustom IC; Bandwidth; Computer architecture; Control systems; Impedance; Logic testing; Memory architecture; Protocols; Random access memory; System testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387351

Filename

1387351