DocumentCode
2448769
Title
Analytic model for area and power constrained optimal repeater insertion
Author
Garcea, G.S. ; Van Der Meijs, N.P. ; Otten, R. H J M
Author_Institution
Fac. of ITS/EE, Delft Univ. of Technol., Netherlands
fYear
2003
fDate
16-18 Sept. 2003
Firstpage
591
Lastpage
594
Abstract
We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a given performance /spl tau//sub crit//K where /spl tau//sub crit/ is the minimum possible delay along a global interconnect, with repeaters inserted, and 0\n\n\t\t
Keywords
circuit optimisation; circuit simulation; integrated circuit design; integrated circuit interconnections; repeaters; analytic formula; delay; global interconnects; global signal; layer assignment; power dissipation; repeater insertion; repeater sizes; segment lengths; silicon device area; width assignment; Closed-form solution; Constraint optimization; Delay; Geometry; Power dissipation; Repeaters; Routing; Silicon devices; Switches; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location
Estoril, Portugal
Print_ISBN
0-7803-7995-0
Type
conf
DOI
10.1109/ESSCIRC.2003.1257204
Filename
1257204
Link To Document