Title :
Continuous representation of the performance of a CMOS library
Author :
Labouygues, B. ; Schindler, J. ; Engels, S. ; Maurine, P. ; Azémard, N. ; Auvergne, D.
Author_Institution :
Univ. de Montpellier, France
Abstract :
In a standard industrial approach the timing performance verification is obtained using a tabular method that necessitates a great amount of simulations. They must specify, for each drive in each logic family: the load, the input slope, the temperature and the supply voltage sensitivity, for each edge, of the transition time and propagation delay. Extending a logical effort like based model of timing performance of CMOS structures we show in this that it is possible to define a specific performance representation allowing a continuous representation of the performance sensitivity of a complete family. We describe the parameter calibration procedure and validate the proposed representation on a 0.13 /spl mu/m process by comparing the performance sensitivity values obtained from electrical simulations performed with the full process model of the foundry.
Keywords :
CMOS logic circuits; circuit simulation; logic design; logic simulation; timing; CMOS library; CMOS structures; continuous representation; electrical simulations; input slope; logic family; parameter calibration procedure; performance sensitivity; propagation delay; standard industrial approach; supply voltage sensitivity; tabular method; timing performance verification; transition time; CMOS logic circuits; Calibration; Foundries; Interpolation; Libraries; Propagation delay; Semiconductor device modeling; Temperature sensors; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257205
