An ultra low-power adiabatic adder embedded in a standard 0.13/spl mu/m CMOS environment

An adiabatic 8-bit ripple carry adder is realized in a 1.2V, 0.13/spl mu/m CMOS technology, to demonstrate the potential of adiabatic logic for low power applications. The layout of the adiabatic back is compatible with static CMOS standard cells. This enables the implementation of large adiabatic circuit blocks with manageable design complexity. At f=20 MHz, the energy is by a factor of 7 lower than in static CMOS, and energy saving is achievable beyond f=100MHz. Interface circuits are presented for the conversion between adiabatic and static CMOS environment. The energy efficiency of a complete adiabatic system is evaluated including a four-phase trapezoidal power clock generator, obtaining an energy saving by a factor of 6 at f=20 MHz.