A small-area high performance 512-point 2-dimensional FFT single-chip processor

Author

Miyamoto, Naoto ; Karnan, L. ; Maruo, Kazuyuki ; Kotani, Koji ; Ohmi, Tadahiro

Author_Institution

Graduate Sch. of Eng., Tohoku Univ., Miyagi, Japan

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

603

Lastpage

606

Abstract

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource saving multi-datapath radix-2/sup 2/ computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.8 /spl times/ 2.8 mm/sup 2/ with CMOS 0.35 /spl mu/m triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensional FFT in 23.2 /spl mu/sec and a 2-dimensional one in only 23.8 msec at 133 MHz operation.

Keywords

CMOS memory circuits; cache storage; fast Fourier transforms; integrated circuit design; memory architecture; 133 MHz; 2 dimensional FFTs; FFT processor core; FFT single chip processor; cached memory architecture; computation element; multidatapath radix; resource saving; single chip 512point FFT processor; single port SRAMs; Computer architecture; Digital signal processing; Discrete Fourier transforms; Equations; Hardware; High performance computing; Multidimensional signal processing; Random access memory; Registers; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257207

Filename

1257207