Programmable and low power VLSI architectures for full search motion estimation in multimedia communications

In this paper a new VLSI architecture for the implementation of an enhanced full-search motion estimator for multimedia terminals is proposed: beyond the usual algorithm, advanced prediction and static priority options are supported to improve the SNR/bit-rate efficiency. The architecture is parametrizable in terms of block size (N) and maximum search area size (p_max) (the latter being also programmable in the range [1, p_max]) thus permitting the implementation of a family of ICs suitable for QCIF, CIF, 4CIF image format processing. Two ASICs were realized on a 0.25 μm, 2.5 V, CMOS technology able to process 30 frames/s QCIF, CIF, 4CIF formats with a search area of -16/+15. The resulting CIF and 4CIF ASICs feature a high throughput vs. area efficiency for a small hardware complexity and power consumption. The former, characterized by a core area of 1.6 mm² , is able to process either QCIF and CIF with a clock frequency of 18 and 72 MHz, respectively, and with an estimated power consumption of about 42 and 170 mW. By exploiting the p programmability, it also processes the QCIF with a clock frequency of about 6 MHz and a power consumption of 15 mW resulting of a great interest for wireless multimedia applications. The 4CIF-ASIC is characterized by a core area of 3.9 mm² with a clock frequency of 105 MHz