Title :
Multiple-bit parallel-CDMA technique for an on-chip interface featuring high data transmission rate, small latency and high noise tolerance
Author :
Shimizu, Shinsah ; Matsuoka, Toshimasa ; Taniguchi, Kenji
Author_Institution :
Dept. of Electron. & Inf. Syst., Osaka Univ., Japan
Abstract :
We proposed a multiple-bit parallel-CDMA (MB/P-CDMA) interface featuring multi-valued voltage swing which enables to send more than one bit data at each clock. The voltage swing at each bus can be reduced to tens of milli-volts because of its high local noise tolerance nature, realizing efficient data transmission through MB/P-CDMA interface. MB/P-CDMA interface had been implemented with 0.35 /spl mu/m CMOS technology.
Keywords :
CMOS digital integrated circuits; code division multiple access; integrated circuit design; multivalued logic; parallel architectures; system buses; 0.35 micron; CMOS technology; MB/P-CDMA; data transmission rate; multiple-bit parallel-CDMA; multivalued voltage swing; noise tolerance; on-chip interface; CMOS technology; Clocks; Data communication; Delay; Information systems; Multiaccess communication; Noise reduction; System-on-a-chip; Transmitters; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257216
