A modular wrapper enabling high speed BIST and repair for small wide memories

This work describes a modular design of a wrapper enabling BIST/BISR for small memories operating as register files or FIFOs in high speed applications such as graphics and networking. The wrapper allows for at-speed test at low overhead and enables a simple repair scheme when millions of bits are used in such memories. The wrapper is intended to provide a standardized interface between memory and test controller, and thus work with any BIST controller, and communication between the two is minimized and at a reduced frequency.