Title :
A New Temporal Logic CTL[k-QDDC] and Its Verification
Author :
Zhu, Jiaqi ; Wang, Hanpin ; Xu, Zhongyuan
Author_Institution :
Sch. of Electron. Eng. & Comput. Sci., Peking Univ., Beijing
fDate :
July 28 2008-Aug. 1 2008
Abstract :
We define a new temporal logic called CTL[k-QDDC]. It extends CTL with the ability to specify branching pasts and quantitative temporal properties by combining CTL with the logic Quantified Discrete-time Duration Calculus (QDDC). The idea of bounded model checking is also used in this logic. Compared to CTL, the added expressive power is necessary for specification and verification of real-time distributed software and hardware systems. We give the syntax and semantics of CTL[k-QDDC], discuss its expressive power, and propose an explicit model checking algorithm for Kripke structure. CTL[k-QDDC] is considered as a foundation of some more complex logics for specifying and verifying continuous-time properties in some appropriate structures.
Keywords :
formal logic; temporal logic; bounded model checking; complex logics; logic quantified discrete-time duration calculus; real-time distributed hardware systems; real-time distributed software; temporal logic; Application software; Automatic logic units; Calculus; Computer applications; Computer science; Hardware; Labeling; Power system modeling; Real time systems; Software systems; branching past; model checking; quantitative;
Conference_Titel :
Computer Software and Applications, 2008. COMPSAC '08. 32nd Annual IEEE International
Conference_Location :
Turku
Print_ISBN :
978-0-7695-3262-2
Electronic_ISBN :
0730-3157
DOI :
10.1109/COMPSAC.2008.53