A dual-band enhanced harmonic rejection filter for modulators in GSM and DCS transmitters

Author

Su, Peng-Un ; Hsu, June-Ming

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Hsin Chu, Taiwan

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

663

Lastpage

666

Abstract

In this paper, a dual-band enhanced harmonic rejection filter along with a quadrature modulator is designed and fabricated in 0.25/spl mu/m CMOS process. This filter is simply a Sallen-Key low pass filter with transmission zeros to provide additional harmonic rejection. The measurement results that the filter significantly suppresses the unwanted harmonics generated by the modulator by more than 30 dB and 40 dB in GSM mode and DCS mode, respectively. This IC operates at 2.7V with current consumption of 4.8mA and 5.7 mA in GSM and DCS mode, respectively.

Keywords

CMOS analogue integrated circuits; harmonics suppression; integrated circuit design; low-pass filters; modulators; notch filters; 0.25 micron; 2.7 V; 4.8 mA; 5.7 mA; CMOS process; DCS transmitters; GSM transmitters; Sallen-Key low pass filter; dual-band harmonic rejection filter; harmonic suppression; quadrature modulators; transmission zeros; Distributed control; Dual band; Filtering theory; Frequency; GSM; Low pass filters; Power harmonic filters; Q factor; Radio transmitters; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257222

Filename

1257222