A hierarchical DFT architecture for chip, board and system test/debug

Author

Njinda, Charles A.

Author_Institution

Procket Networks, Milpitas, CA, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1061

Lastpage

1071

Abstract

This work presents the Procket DFT architecture which is developed to improve manufacturability (time-to-market, high quality and ease of chip/board/system bring-up) thus reducing the time for chip ramp and initial system bring-up. Common DFT structures are used on all chips in the family and a similar process is used to access all on-chip DFT structures from the system. This architecture allows for reconfigurable scan chains, which includes parallel chains for tester access, and various sections of the chains during board/system bring up to allow for easy diagnosis. Access to all debug features is via the IEEE 1149.1 ports which allows the same software to be used for chip, board and system debug.

Keywords

IEEE standards; design for testability; integrated circuit testing; network routing; reconfigurable architectures; system-on-chip; IEEE 1149.1 ports; Procket DFT architecture; board debug; board test; chip debug; chip test; hierarchical DFT architecture; manufacturability; on-chip DFT structures; reconfigurable scan chains; system debug; system test; High speed optical techniques; Logic devices; Logic testing; Optical buffering; Optical packet switching; Power system reliability; Pulp manufacturing; System testing; System-on-a-chip; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387379

Filename

1387379