DocumentCode
2449494
Title
A low power and high speed Viterbi decoder chip for WLAN applications
Author
Lin, Chien-Ching ; Wu, Chia-Cho ; Lee, Chen-Yi
Author_Institution
Dept. of Electron. & Eng., Nat. Chiang Tung Univ., Hsinchu, Taiwan
fYear
2003
fDate
16-18 Sept. 2003
Firstpage
723
Lastpage
726
Abstract
This paper presents a 166Mb/s, 64-state, radix-4, 16-level soft decision Viterbi decoder for high speed WLAN applications. With the path merging and trace forward techniques, the memory read operations are reduced to save power consumption. A test chip is fabricated in 0.35/spl mu/m IP4M CMOS process, and can achieve the maximum throughput rate of 166Mbit/s under 3.3V. The measured power consumption is below 55mW under 166Mb/s throughput rate at 2.2V.
Keywords
CMOS digital integrated circuits; Viterbi decoding; high-speed integrated circuits; integrated circuit design; low-power electronics; wireless LAN; 0.35 micron; 166 Mbit/s; 2.2 V; 3.3 V; 55 mW; Viterbi decoder chip; WLAN applications; memory read operations; path merging; power consumption; soft decision decoder; trace forward; CMOS process; Decoding; Energy consumption; Merging; Power measurement; Semiconductor device measurement; Testing; Throughput; Viterbi algorithm; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location
Estoril, Portugal
Print_ISBN
0-7803-7995-0
Type
conf
DOI
10.1109/ESSCIRC.2003.1257237
Filename
1257237
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