A high-resolution flash time-to-digital converter and calibration scheme

Flash time-to-digital converters (TDCs) are well-suited for use in on-chip timing measurement systems because they can be operated at high speeds, offer low test time, and are relatively easy to integrate. However, clock jitter in modern integrated circuits is often on the same order of magnitude as the temporal resolution of the TDC itself. Therefore, techniques are required to increase the resolution of these devices, while ensuring timing accuracy. This work presents a high-resolution flash TDC that exploits the random offsets on flip-flops or arbiters to perform time quantization. It also describes a novel technique based on additive temporal noise to accurately calibrate the measurement device. Simulation and experimental results reveal that the latter method can calibrate the high-resolution flash TDC down to 5 ps within reasonable error limits. In addition, accurate timing measurement of jitter below 14 ps has been experimentally validated using a high-resolution flash TDC fabricated in a 0.18-μm CMOS process.