• DocumentCode
    2449753
  • Title

    Efficient exhaustive verification of the Collatz conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs

  • Author

    Ito, Yasuaki ; Nakano, Koji

  • Author_Institution
    Dept. of Inf. Eng., Hiroshima Univ., Higashi-Hiroshima, Japan
  • fYear
    2010
  • fDate
    19-23 April 2010
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    Consider the following operation on an arbitrary positive number: if the number is even, divide it by two, and if the number is odd, triple it and add one. The Collatz conjecture asserts that, starting from any positive number m, repeated iteration of the operations eventually produces the value 1. The main contribution of this paper is to present an efficient implementation of a coprocessor that performs the exhaustive search to verify the Collatz conjecture using a DSP48E Xilinx Virtex-5 blocks, each of which contains one multiplier and one adder. The experimental results show that, our coprocessor can verify 3.88 × 108 64-bit numbers per second.
  • Keywords
    field programmable gate arrays; formal verification; Collatz conjecture; DSP48E blocks; Xilinx Virtex-5 FPGAs; coprocessor; efficient exhaustive verification; field programmable gate array; Field programmable gate arrays; Collatz conjecture; DSP blocks; FPGA Implementation; Hardware Algorithm; block RAMs;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on
  • Conference_Location
    Atlanta, GA
  • Print_ISBN
    978-1-4244-6533-0
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2010.5470837
  • Filename
    5470837