Reducing power consumption in memory ECC checkers

Author

Ghosh, Shalini ; Basu, Sugato ; Touba, Nur A.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1322

Lastpage

1331

Abstract

A method is proposed for reducing power consumption in memory ECC checker circuitry that provides SEC-DED. The degrees of freedom in selecting the parity check matrix are used to minimize power with little or no impact on area and delay. The power minimization method is applied to two popular SEC-DED codes: standard Hamming codes and odd-column-weight Hsiao codes. Experiments on actual memory traces of Spec and MediaBench benchmarks indicate that considering power in addition to area and delay when selecting the parity check matrix can result in power reductions of up to 27% for Hsiao codes and up to 41% for Hamming codes.

Keywords

Hamming codes; error correction codes; integrated memory circuits; matrix algebra; minimisation; parity check codes; power consumption; degrees of freedom; double error correcting codes; memory ECC checker circuitry; odd column weight Hsiao codes; parity check matrix; power consumption reduction; power minimization method; single error correcting codes; standard Hamming codes; Circuits; Computer errors; Costs; Delay; Energy consumption; Error correction codes; Parity check codes; Power engineering and energy; Power engineering computing; Rails;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387407

Filename

1387407