A FPGA-based Dewavefront Array Prototype Implementing the Quadrant Interlocking Factorization Method

The systolic processing offers the possibility of solving a large number of standard problems on multicellular computing devices with autonomous cells (processing elements - PEs). The resulting systolic arrays exploit the underlying parallelism of many computationally intensive problems and offer a vital and effective way of handling them. Advances in technology and especially in VLSI and FPGA have an ongoing contribution to the evolution of systolic and wavefront arrays. The concept of wavefront arrays differentiates from that of the systolic arrays in the following: the wavefront arrays consist of PEs with varying computation time allowed and the overall control is achieved by handshaking signals amongst the cells (instead of a common clock). Herein, a FPGA-based de(double ended) wavefront array prototype implementing the factorization stage of the quadrant interlocking factorization - QIF (Butterfly) method is presented and the corresponding time-complexities achieved are discussed