Testing high resolution ADCs with low resolution/accuracy deterministic dynamic element matched DACs

Author

Jiang, Hanjun ; Olleta, Beatriz ; Chen, Degang ; Geiger, Randall L.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1379

Lastpage

1388

Abstract

This work presents a deterministic dynamic element matching (DDEM) approach which is applied to low precision DACs to generate stimulus signals for ADC testing. Both simulation results and experimental results from a fabricated DDEM DAC are presented to verify the performance. The ADC testing performance of an 8-bit DDEM DAC (linearity less than 5 bits without DDEM) is comparable to or better than the best results reported in the literature using on-chip linear ramp generators. The DDEM technique offers great potential for use in both production test and built-in-self-test(BIST) environments.

Keywords

analogue-digital conversion; built-in self test; digital-analogue conversion; integrated circuit testing; mixed analogue-digital integrated circuits; production testing; ramp generators; ADC testing; BIST environments; DAC; built-in-self-test; deterministic dynamic element matching; on-chip linear ramp generators; production test; stimulus signals generation; Analog-digital conversion; Built-in self-test; Circuit testing; Costs; Digital-analog conversion; Linearity; Logic; Production; Signal generators; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387413

Filename

1387413