DocumentCode :
2450522
Title :
Real-time 3DTV system for autostereoscopic displays
Author :
Yao, Shao-Jun ; Jin, Peng-Fei ; Fu, Hang ; Wang, Liang-Hao ; Li, Dong-Xiao ; Zhang, Ming
Author_Institution :
Inst. of Inf. & Commun. Eng., Zhejiang Univ., Hangzhou, China
fYear :
2012
fDate :
16-18 July 2012
Firstpage :
621
Lastpage :
626
Abstract :
This Paper focuses on the real-time implementation of 3DTV system, of which the core algorithms are stereo matching and multi-view rendering. The former algorithm is specially designed for the generation of high-quality disparity map on the graphics processing unit (GPU) through CUDA (Compute Unified Device Architecture) API, it is structured in a way that exposes as much data parallelism as possible and the power of shared memory and data parallel programming in GPU is exploited. The latter algorithm is specially designed in a new hardware architecture consisting of dual parallel DIBR, merging, hole filling, and synthesis, for the generation of multi-view images on the FPGA. We make the communication between PC and FPGA across network. Experiment results show that, for each 450 × 375 video with 60 disparity levels, stereo matching achieve about 16 frames per second on an NVIDIA Tesla C2050 graphics card and speed can be up to 30 frames per second after doing downsapling. Multi-view rendering can achieve 30 frames per second for processing full HD (1920 × 1080) video on Xilinx Virtex IV XC4VSX25.
Keywords :
application program interfaces; field programmable gate arrays; graphics processing units; image matching; parallel architectures; parallel programming; rendering (computer graphics); shared memory systems; stereo image processing; three-dimensional displays; three-dimensional television; API; CUDA; FPGA; GPU; NVIDIA Tesla C2050 graphics card; Xilinx Virtex IV XC4VSX25; autostereoscopic displays; compute unified device architecture; data parallel programming; data parallelism; dual parallel DIBR; full HD video processing; graphics processing unit; hardware architecture; high-quality disparity map; hole filling; merging; multiview images; multiview rendering; real-time 3DTV system; shared memory; stereo matching; Acceleration; Cameras; Computer architecture; Field programmable gate arrays; Graphics processing units; Hardware; Rendering (computer graphics);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Audio, Language and Image Processing (ICALIP), 2012 International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4673-0173-2
Type :
conf
DOI :
10.1109/ICALIP.2012.6376691
Filename :
6376691
Link To Document :
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