Achieving quality levels of 100 DPM: it´s possible... but roll up your sleeves and be prepared to do some work

Author

Nigh, Phil

Author_Institution

IBM Technol.& Syst. Group, Essex Junction, VT, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1420

Abstract

The methods that are required to meet aggressive DPM objectives are thorough delay tests, very high coverage test patterns, IDDQ test, RAM tests, multiple temperature tests, functional tests, statistical methods, parametric test limits, customer specific tests, DFT. The trade-offs of driving quality levels to <100 DPM include yield loss, schedule impacts, engineering costs.

Keywords

design for testability; integrated circuit design; integrated circuit testing; quality control; statistical analysis; DFT; IDDQ test; RAM tests; customer specific tests; delay tests; engineering costs; functional test; multiple temperature tests; parametric test limits; quality levels; schedule impacts; statistical methods; very high coverage test patterns; yield loss; Costs; Delay; High speed integrated circuits; Integrated circuit testing; Job shop scheduling; Manufacturing; Production; Statistical analysis; System testing; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387428

Filename

1387428

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2450759