DocumentCode
2450830
Title
Testing in a high volume DSM environment
Author
Storey, Thomas
Author_Institution
BAE Syst., Manassas, VA, USA
fYear
2004
fDate
26-28 Oct. 2004
Firstpage
1422
Abstract
DSM manufacturing is expensive. It has been estimated that it costs in excess of &rlarr2; to build a 90nm line. DSM designs are much more susceptible to topological based deformations. Finally, in the DSM environment, it becomes increasingly difficult to separate design vs. process marginalities. Clearly one goal of design for manufacturability is to avoid such sensitivities where identified. This requires an in depth knowledge of the process "sweet spots," acquired initially via test sites especially developed with this objective, followed by focussed diagnosis of the product itself. Since it is unrealistic to assume that ATE is an economically viable solution for the speed requirements, at-speed BIST techniques prevails.
Keywords
automatic test equipment; built-in self test; design for manufacture; integrated circuit testing; ATE; at-speed BIST techniques; deep sub micron design; deep sub micron environment; design for manufacturability; testing; Circuit testing; Costs; Environmental economics; Graphics; Inspection; Manufacturing; Microprocessors; Semiconductor device manufacture; System testing; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN
0-7803-8580-2
Type
conf
DOI
10.1109/TEST.2004.1387430
Filename
1387430
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