ATE value add through open data collection panel position paper for "Dude! where\´s my data? - cracking open the hermetically sealed tester"

The exponential rising cost of semiconductor manufacturing has finally caused a slowing of Moore´s law. The industry is responding with platform ASICs, FPGAs and mask shuttles for lowering cost. In this environment, semiconductor test cannot afford to continue in an ever-increasing cost spiral as a limited-value added quality step in the flow. With increasing complexity of processes and circuitry, the traditional tools and techniques for yield enhancement are becoming less effective, more time consuming and more costly. With the increasing use of foundries, fabless companies do not have access to the fab data that used to drive yield enhancement efforts. The fault isolation and impact quantification information must come from die sort and final test.