Title :
A simulation system for capacitance variation by CMP process including defocus effect
Author :
Ohta, T. ; Fujinaga, M. ; Kimura, M. ; Wada, T. ; Nishi, K.
Author_Institution :
Semicond. Leading Edge Technol. Inc., Yokohama, Japan
Abstract :
We have developed a total interconnect simulation system including a CMP model. The capacitance variation due to pattern width difference from focus effects on a globally nonuniform surface by CMP is simulated with this system. The paper also shows a way to reduce the capacitance variation due to CMP processes derived from these simulations
Keywords :
capacitance; chemical mechanical polishing; integrated circuit interconnections; integrated circuit modelling; semiconductor process modelling; CMP; CMP model; CMP process; CMP processes; capacitance variation; capacitance variation reduction; defocus effect; focus effects; globally nonuniform surface; pattern width difference; simulation system; simulations; total interconnect simulation system; Capacitance; Delay; Focusing; Large scale integration; Lead compounds; Logic; Noise reduction; Parameter extraction; Surfaces; Wiring;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-6279-9
DOI :
10.1109/SISPAD.2000.871218
