Options for high-volume test of multi-Gb/s ports

Author

Johnson, John C.

Author_Institution

Test Platform Archit. & Dev., Intel Corp., USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1435

Abstract

Devices with multi-GB/s ports from a variety of suppliers are shipping in high-volume today. Common port standards such as PCI Express are proliferating along with specialty ports. The number of lanes in multi-GB/s port can usually be scaled to increase bandwidth. The use of this serial/parallel port technology is growing as its bandwidth scaling, PCB trace out. Traditional SERDES devices with only 1 or 2 lanes had most yield fallout in the high-speed serial portion of the design. The industry responded with ATE instruments to expose those defects. Physical layer compliance testing is always a challenge and becomes overwhelming when coupled with multiple port types. In many cases, logic test patterns are applied through a multi-GB/s port at speed. The very high speed interfaces shows non-deterministic logic behavior.

Keywords

automatic test equipment; logic testing; ATE instruments; PCB trace out; PCI Express; SERDES devices; bandwidth scaling; high-volume test; logic test patterns; multiports; nondeterministic logic behavior; physical layer compliance testing; serial-parallel port technology; very high speed interfaces; Bandwidth; Bit error rate; Costs; Instruments; Jitter; Logic devices; Logic testing; Physical layer; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387443

Filename

1387443