Is "Heisenberg uncertainty principle" hold for designing and testing multiple Gb/s ICs ?

Author

Li, Mike

Author_Institution

Wavecrest, San Jose, CA, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1436

Abstract

In This work, specific challenges faced in design and test multiple Gb/s ICs when cost, performance, and volume constraints are imposed simultaneously is focused and plausible solutions are discussed. The economical version of Heisenberg uncertainty principle for the relationship between cost and performance is in contradicting with the simple technology scaling approach, unless: a) new technologies are developed to meet low cost, high volume, high performance requirements; b) cost and performance requirements are relaxed. The nature of statistical JNB (jitter, noise, bit error rate), low cost, high volume, and high performance requirements suggest that it is hard to skip JNB in any processes in designing and manufacturing multiple Gb/s commodity ICs. By optimizing the relative role and cost for JNB in processes of DS (design simulation), DCVT (design characterization and verification test process), and HVMT (high volume manufacturing test) overall cost is minimized.

Keywords

error statistics; indeterminancy; integrated circuit design; integrated circuit testing; jitter; production testing; Heisenberg uncertainty principle; bit error rate; cost minimisation; design characterization; design simulation; design verification; high volume manufacturing test; integrated circuit design; integrated circuit testing; jitter; noise; statistical process; Bit error rate; Clocks; Computer architecture; Costs; Crosstalk; Jitter; Manufacturing processes; Testing; Timing; Uncertainty;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387444

Filename

1387444