Title :
CHAMPS (chemical-mechanical planarization simulator)
Author :
Kim, Kyung-Hyun ; Yoo, Kwang-Jae ; Kyung-Hyun Kim ; Yoon, Bo-Yeon ; Park, Young-Kwan ; Ha, Sang-Rok ; Kong, Jeong-Taek
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyungki-Do, South Korea
Abstract :
Simulation of chemical-mechanical polishing is important because the chip-level planarity and wafer-level uniformity dependent on many dynamic factors are difficult to control. CHAMPS (chemical mechanical planarization simulator) has been developed for predicting and optimizing the thickness distribution after the CMP process using the chip level pattern density and an elastic spring model including equipment parameters. In this work, the results of CMP simulation are shown to agree well with the measured data. This simulator can be used to optimize CMP process conditions and to generate design rules for filling dummy patterns which are used to improve planarity and uniformity
Keywords :
chemical mechanical polishing; integrated circuit design; integrated circuit measurement; optimisation; semiconductor process modelling; surface topography; CHAMPS chemical-mechanical planarization simulator; CMP process; CMP process conditions optimization; CMP simulation; chemical-mechanical polishing simulation; chip level pattern density; chip-level planarity; design rules; dummy pattern filling; dynamic process factors; elastic spring model; equipment parameters; measured data; planarity; thickness distribution optimization; thickness distribution prediction; uniformity; wafer-level uniformity; Computer aided engineering; Layout; Monitoring; Planarization; Predictive models; Research and development; Semiconductor device measurement; Semiconductor device modeling; Slurries; Springs;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-6279-9
DOI :
10.1109/SISPAD.2000.871223