Title :
Improved device technology evaluation and optimization
Author :
Connelly, Daniel ; Foisy, Mark
Author_Institution :
DigitalDNA Labs., Motorola Inc., Austin, TX, USA
Abstract :
The conventional IDsat-IDL (where IDsat is drain current for VDS=VGS=VDD with VBS=0, and IDL is drain current for VDS =VDD, with VGS=VBS=0) curve falls short in predicting which of two technology options will result in the best circuit performance. Here, for the first time, we demonstrate an improved evaluation method which accounts for process variation and leakage current budgeting for a target gate length. By using iteration or interpolation to compare tuned technologies, and by evaluating leakage and drive currents from the appropriate portions of their distribution curves, more effective optimization is achieved, giving stronger weight to robust device design
Keywords :
circuit CAD; circuit analysis computing; circuit optimisation; current distribution; integrated circuit design; integrated circuit technology; interpolation; iterative methods; leakage currents; circuit performance; current distribution curves; device technology evaluation; device technology optimization; drain current; drive current; evaluation method; interpolation; iteration; leakage current; leakage current budgeting; optimization; process variation; robust device design; target gate length; technology options; tuned technologies; Appropriate technology; Circuit optimization; Design optimization; Drives; Electron devices; Interpolation; Leakage current; Robustness; Transconductance; Voltage;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-6279-9
DOI :
10.1109/SISPAD.2000.871231
