Investment vs. yield relationship for memories and IP in SoC

Author

Reynick, Joseph A.

Author_Institution

eSilicon Corp., Allentown, PA, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1446

Abstract

Today´s large SoC designs are using higher percentages of outsourced IP and manufacturing than in the past. At the same time, native IC yield is shrinking due to higher memory defect densities and higher percentages of memory. Today, memory repair and redundancy, along with ECC methods are the prevalent means for active yield remediation. Methods need to emerge for standard logic. From a business perspective, there is a paradigm shift to outsourcing IP and manufacturing. This raises several important questions. How can yield be maximized? What are the limitations of active yield improvement? What is the fastest path to a solution if there is a yield issue? Who owns the native yield? Who owns the test yield?.

Keywords

integrated circuit design; integrated circuit yield; integrated logic circuits; integrated memory circuits; investment; redundancy; system-on-chip; ECC methods; IC yield; IP outsourcing; SoC designs; digital circuits; higher memory percentage; investment; memory defect density; memory redundancy; memory repair; standard logic; yield relationship; Built-in self-test; Costs; Design for testability; Design optimization; Digital integrated circuits; Investments; Libraries; Logic testing; Manufacturing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387454

Filename

1387454