Modeling of Elevated Temperatures Impact on Single Event Transient in Advanced CMOS Logics Beyond the 65-nm Technological Node

This work presents the modeling of the impact of elevated temperatures on the SET occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The calculations are performed by the combined MUSCA SEP3 platform and Cadence simulations. Comparisons between predictions and experimental data of the impact of temperature on the SET cross section(s) and the SET pulse-width are consistent. A different behavior between n-MOS and p-MOS transistors are exhibited at elevated temperatures. A basic radiation mitigation technique is presented and evaluated with the aim to reduce the SET occurrence and characteristics. The die-shrink to 28-nm is also investigated with the goal to investigate the impact of the technology scale on the charge sharing phenomena at elevated temperatures. The interest of this work is to propose a modeling of the behavior of CMOS devices at high temperatures with the aim to help designers to anticipate the soft error sensitivity taking into account the technological scale.