A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation

Author

Wei Deng ; Musa, Afiqah ; Siriburanon, Teerachot ; Miyahara, Masaya ; Okada, Kenichi ; Matsuzawa, Akira

Author_Institution

Dept. Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2014

fDate

20-23 Jan. 2014

Firstpage

21

Lastpage

22

Abstract

This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm² resulting in the best performance-area trade-off system presented up-to-date.

Keywords

CMOS digital integrated circuits; calibration; clocks; digital phase locked loops; low-power electronics; CMOS process; FOM; all-digital background calibration system; compact low power dual-loop injection-locked PLL; frequency 1.2 GHz; low jitter dual-loop injection-locked PLL; on-chip clock generation; performance-area trade-off system; power 0.97 mW; size 65 nm; time 0.7 ps; Calibration; Clocks; Jitter; Phase locked loops; Radiation detectors; Temperature measurement; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific

Conference_Location

Singapore

Type

conf

DOI

10.1109/ASPDAC.2014.6742854

Filename

6742854