DocumentCode
245219
Title
A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor
Author
Ikeda, Shoji ; Kamimura, Taeko ; Sangyeop Lee ; Ito, H. ; Ishihara, Noboru ; Masu, Kazuya
Author_Institution
Solutions Res. Lab., Tokyo Inst. of Technol., Yokohama, Japan
fYear
2014
fDate
20-23 Jan. 2014
Firstpage
23
Lastpage
24
Abstract
This paper proposes an ultra-low-power 5.5-GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD), which is calibrated by digital circuits, and linearity-compensated varactors for low supply-voltage operation. The proposed PLL was fabricated in 65nm CMOS. It shows a 1-MHz-offset phase noise of -106 dBc/Hz and the total power consumption of 950μW at 5.5 GHz.
Keywords
CMOS integrated circuits; digital phase locked loops; frequency dividers; low-power electronics; varactors; CMOS; digital circuits; digitally-calibrated ILFD; divide-by-4 injection-locked frequency divider; frequency 5.5 GHz; linearity-compensated varactors; power 950 muW; size 65 nm; ultra-low-power PLL; Phase locked loops; Phase noise; Radiation detectors; Threshold voltage; Varactors; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific
Conference_Location
Singapore
Type
conf
DOI
10.1109/ASPDAC.2014.6742855
Filename
6742855
Link To Document