Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints

Sub-50 nm CMOS technologies are affected by significant variability which causes power and performance variations among nominally similar cores in MPSoC platforms. This undesired heterogeneity threatens execution predictability and energy efficiency. We propose two techniques to allocate sets of barrier-synchronized tasks (representative of a wide class of image processing workloads) onto variability-affected MPSoCs. The first technique models allocation as an ILP and achieves optimal results, but requires an off-line solver. The second techniques adopt a two-stage heuristic approach, and it can be adapted to work on-line. We tested our approach on the virtual prototype of a next-generation industrial multi-core platform. Experimental results demonstrate that our approach minimizes deadline violations while increasing energy efficiency.