Title :
STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures
Author :
Xiaoxiao Liu ; Yong Li ; Yaojun Zhang ; Jones, Alex K. ; Yiran Chen
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA
Abstract :
Translation lookaside buffer (TLB) was recently introduced into modern graphics processing unit (GPU) architectures to support virtual memory addressing. Compared to CPUs, the performance of GPUs is more sensitive to the capacity of TLBs because of heavier memory accesses. However, large SRAM cell area greatly limits the implementable capacity of conventional SRAM-based TLBs. In this work, we propose using STT-RAM to construct TLBs in light of the unique memory access pattern in GPUs, i.e., infrequent data updates. STT-RAM TLB can replace its same-area SRAM counterpart with greater capacity, similar read performance and lower energy consumption. As an optimization of STT-RAM TLB, we further propose a STT-RAM-based dynamically-configurable TLB (STD-TLB) by leveraging differential sensing technique. STD-TLB can switch between high-capacity mode and high-performance mode on-the-fly based on real-time application needs. Our experiments show that compared to SRAM TLB, standard STT-RAM TLB improves the performance and energy delay product of GPU address translation by 32% and 75%, respectively, while STD-TLB achieves additional 15% and 13% improvements over standard STT-RAM TLB.
Keywords :
buffer storage; graphics processing units; random-access storage; GPU architectures; SRAM cell area; SRAM-based TLB; STD-TLB; STT-RAM TLB optimization; STT-RAM-based dynamically-configurable TLB; differential sensing technique; graphics processing unit architectures; high-capacity mode; high-performance mode on-the-fly; infrequent data updates; memory access pattern; real-time application needs; translation lookaside buffer; virtual memory addressing; Benchmark testing; Computer architecture; Graphics processing units; Microprocessors; Random access memory; Sensors; Standards;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific
Conference_Location :
Singapore
DOI :
10.1109/ASPDAC.2014.6742915