DocumentCode :
2454770
Title :
Modeling techniques and tests for partial faults in memory devices
Author :
AL-Ars, Zaid ; Van de Goor, Ad J.
Author_Institution :
Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
fYear :
2002
fDate :
2002
Firstpage :
89
Lastpage :
93
Abstract :
It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior This means that, given a fault model, it should be possible to construct a test that ensures detecting the modeled fault. This paper shows that some faults, called partial faults, are particularly difficult to detect. For these faults, more operations are required to complete their fault effect and to ensure detection. The paper also presents fault analysis results, based on defect injection and simulation, where partial faults have been observed. The impact of partial faults on testing is discussed and a test to detect these partial faults is given
Keywords :
DRAM chips; fault diagnosis; integrated circuit modelling; integrated circuit testing; logic testing; DRAMs; completing operations; defect injection; fault analysis results; fault model; memory devices; modeling techniques; partial faults; Analytical models; Boolean functions; Data structures; Fault detection; Information technology; Random access memory; Resource description framework; Testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
ISSN :
1530-1591
Print_ISBN :
0-7695-1471-5
Type :
conf
DOI :
10.1109/DATE.2002.998254
Filename :
998254
Link To Document :
بازگشت