• DocumentCode
    2454848
  • Title

    AccuPower: an accurate power estimation tool for superscalar microprocessors

  • Author

    Ponomarev, Dmitry ; Kucuk, Gurhan ; Ghose, Kanad

  • Author_Institution
    Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    124
  • Lastpage
    129
  • Abstract
    This paper describes the AccuPower toolset-a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hardware level and cycle level microarchitectural simulator and energy dissipation coefficients gleaned from SPICE measurements of actual CMOS layouts of critical datapath components. Transition counts can be obtained at the level of bits within data and instruction streams, at the level of registers, or at the level of larger building blocks (such as caches, issue queue, reorder buffer function units). This allows for an accurate estimation of switching activity at any desired level of resolution. The toolsuite implements several variants of superscalar datapath designs in use today and permits the exploration of design choices at the microarchitecture level as well as the circuit level, including the use of voltage and frequency scaling. In particular the AccuPower toolsuite includes detailed implementations of currently used and proposed techniques for energy/power conservations including techniques for data encoding and compression, alternative circuit approaches, dynamic resource allocation and datapath reconfiguration. The microarchitectural simulation components of AccuPower can be used for accurate evaluation of datapath designs in a manner well beyond the scope of the widely-used Simplescalar tools
  • Keywords
    SPICE; circuit simulation; integrated circuit layout; low-power electronics; microprocessor chips; parallel architectures; AccuPower; CMOS layouts; SPICE measurements; VLSI layout; caches; critical datapath components; cycle level microarchitectural simulator; data compression; data encoding; datapath reconfiguration; dynamic resource allocation; energy dissipation coefficients; frequency scaling; function units; hardware level microarchitectural simulator; instruction streams; issue queue; power conservation; power dissipation; power estimation tool; reorder buffer; simulation tools; superscalar datapath designs; superscalar microprocessors; switching activity; transition counts; voltage scaling; Circuits; Dynamic voltage scaling; Energy dissipation; Energy measurement; Frequency; Hardware; Microarchitecture; Microprocessors; Power dissipation; SPICE;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1471-5
  • Type

    conf

  • DOI
    10.1109/DATE.2002.998259
  • Filename
    998259