SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network

One of the design challenges for the emerging 3D ICs is the power integrity. With multiple dies stacked vertically, the voltage droop may result in severe power integrity issues. In this paper, we first analyze the impact of application behaviors on voltage droop in a 3D power supply network (PDN) and observe that voltage droop is extremely imbalanced either across different layers or among the cores in the same layer. Based on the observation, we propose Swimming Lane, a hardware/software co-design method with two key schemes: (1) Mitigating the interference among different dies via a layer-independent scheme, and (2) balancing the intra-layer voltage droop and reducing the worst-case margin via OS scheduling. Compared to conventional designs, our method can reduce power consumption by 18%, worst-case voltage droops by 13%, and the number of voltage violations by 40%.