Title :
S-CFG: a representation model for system synthesis
Author :
Curatelli, E. ; Mangeruca, L. ; Chirico, M.
Author_Institution :
DIBE, Genoa Univ., Italy
fDate :
29 Sep-2 Oct 1998
Abstract :
A representation model (S-CFG, system control flow graph) for system specification and synthesis is described, which is organized in two levels (block and thread). The management of the control/data flow information is performed through the use of control/data flow graphs owning: 1) hierarchical definition of control edges, 2) suitable management of timing constraints through timing edges, 3) definition of data communication through data edges. The use of hierarchy in control edges makes it possible to define in a powerful and compact way the execution semantics of the S-CFG
Keywords :
circuit CAD; data flow graphs; formal specification; hardware-software codesign; S-CFG; control edges; control information; data communication; data flow graphs; data flow information; execution semantics; hierarchical definition; management; representation model; system control flow graph; system specification; system synthesis; timing constraints; timing edges; Communication system control; Concurrent computing; Context modeling; Control system synthesis; Flow graphs; Hardware design languages; Power system management; Power system modeling; Timing; Yarn;
Conference_Titel :
Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI International Symposium on
Conference_Location :
Pisa
Print_ISBN :
0-7803-4900-8
DOI :
10.1109/ISSSE.1998.738092
