Title :
La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application
Author :
Park, C.S. ; Yang, J.W. ; Hussain, M.M. ; Kang, C.Y. ; Huang, J. ; Sivasubramani, P. ; Park, C. ; Tateiwa, K. ; Harada, Y. ; Barnett, J. ; Melvin, C. ; Bersuker, G. ; Kirsch, P.D. ; Lee, B.H. ; Tseng, H.-H. ; Jammy, R.
Author_Institution :
SEMATECH, Austin, TX, USA
Abstract :
This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32 nm LSTP and HP applications. The 32 nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32 nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.
Keywords :
MOSFET; high-k dielectric thin films; lanthanum; La; gate length transistor; high-k-metal gate stack devices; metal electrode; metal-high-k nMOSFET; size 32 nm; Annealing; Capacitance-voltage characteristics; Data mining; Dry etching; Electrodes; Fluctuations; High K dielectric materials; High-K gate dielectrics; Jamming; MOSFET circuits;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2784-0
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2009.5159290
