Title :
Scaling challenges of MOSFET for 32nm node and beyond
Author_Institution :
Fujitsu Microelectron. Ltd., Kuwana, Japan
Abstract :
Scaling challenges for MOSFET fabrication process with design rule of 32 nm and below will be reviewed. This paper will especially focus on the scaling issues of conventional planar bulk CMOS technology and discuss about multiple stress engineering, junction engineering and high-k/metal gate stack as key technology boosters to enhance CMOS performance with scaled dimensions.
Keywords :
CMOS integrated circuits; MOSFET; nanoelectronics; CMOS performance enhancement; MOSFET fabrication process; MOSFET scaling challenge; high-k-metal gate stack technology; junction engineering; multiple stress engineering; size 32 nm; Annealing; CMOS technology; Compressive stress; Fabrication; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Pulse shaping methods; Tensile stress; Thermal degradation;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2784-0
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2009.5159296
