DocumentCode
2455345
Title
Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification
Author
Ciesielski, Maciej J. ; Kalla, Priyank ; Zhihong Zheng ; Rouzeyre, Bruno
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear
2002
fDate
2002
Firstpage
285
Lastpage
289
Abstract
This paper presents a new, compact, canonical graph-based representation, called Taylor expansion diagrams (TEDs). It is based on a general non-binary decomposition principle using Taylor series expansion. It can be exploited to facilitate the verification of high-level (RTL) design descriptions. We present the theory behind TEDs, comment upon its canonicity property and demonstrate that the representation has linear space complexity. Its application to equivalence checking of high-level design descriptions is discussed
Keywords
circuit CAD; circuit complexity; graph theory; high level synthesis; series (mathematics); TEDs; Taylor expansion diagrams; Taylor series expansion; canonicity property; compact canonical representation; design verification; digital designs; equivalence checking; general nonbinary decomposition principle; high-level RTL design verification; high-level design descriptions; linear space complexity; symbolic verification; Application software; Automatic control; Boolean functions; Control systems; Digital arithmetic; Formal verification; Logic design; Robots; Robustness; Taylor series;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location
Paris
ISSN
1530-1591
Print_ISBN
0-7695-1471-5
Type
conf
DOI
10.1109/DATE.2002.998286
Filename
998286
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