Double patterning interactions with wafer processing, OPC and physical design flows

In this work we study interactions of double patterning technology (DPT) with lithography, masks synthesis and physical design flows for the 22 nm device node. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193 nm lithography tools. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.