Title :
Recent developments in NAND flash scaling
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
NAND Flash cell has scaled by Gtl000X in area since its inception over 2 decades ago. There are, however, several scaling challenges that need to be overcome to continue scaling below the 3X node. Many evolutionary and revolutionary approaches, such as high-K inter-poly-dielectric (IPD), engineered tunnel barriers, trap based charge storage devices, as well as 3-D structures are being pursued to overcome these scaling challenges. The paper will discuss some of these challenges and related developments.
Keywords :
NAND circuits; flash memories; high-k dielectric thin films; scaling circuits; NAND flash scaling; evolutionary approaches; high-K inter-poly-dielectric; revolutionary approaches; trap based charge storage devices; tunnel barriers; High K dielectric materials; High-K gate dielectrics;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2784-0
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2009.5159310
