An Area Optimized Direct Digital Frequency Synthesizer Based on Improved Hybrid CORDIC Algorithm

This paper proposes a novel implementation technique for area optimized direct digital frequency synthesizer (DDFS) based on improved hybrid coordinate rotation digital computer (CORDIC) algorithm. Researches at algorithmic level focus on how to reduce algorithm complexity, such as cutting down all of rotational phase decision circuits and multipliers, simplifying scale factor with soft hardware co-design approach. At architectural level, the pipeline multilevel loop iteration implementation proposal is adopted for reusing shifting and adder-subtractor components highly. The design has been successfully integrated in a channel demodulation module of broadband network system on chip (SoC) platform. With generality, the technique can be also applied to other wireless network communication system.